Project Management
EDAcation adds a new "EDA" button to the left sidebar of VSCode. Clicking this button will open the main interface of EDAcation, from where you can manage your projects, input / output files, execute tasks and more.
Tool Installation
EDAcation depends on external tools (such as Yosys and Nextpnr) for most of its core functionality. One of EDAcation's main features is its ability to automatically install and manage these tools. This means that you don't have to worry about manually installing these tools or managing their versions, as EDAcation will take care of all of that for you.
RTL
EDAcation allows you to generate RTL diagrams from your design files, which can help you visualize the structure of your design and understand how different modules are connected. The RTL generation task will take your design files as input and produce RTL files as output, which can be viewed directly in VSCode or with third-party applications.
Synthesis
EDAcation allows you to synthesize your design files, which is the process of converting your high-level design description (such as Verilog or VHDL) into a lower-level representation that can be implemented on hardware. The synthesis task will take your design files as input and produce a LUT file as output, which can be viewed directly in VSCode. The synthesis task must be executed before you can execute the place and route task, as it generates the necessary files for place and route to work.
Place & Route
EDAcation allows you to perform place and route on your design files, which is the process of mapping your synthesized design onto the physical resources of the target FPGA. The place and route task will take the output from the synthesis task as input and produce a Nextpnr file as output, which can be viewed directly in VSCode. The place and route task must be executed after you have executed the synthesis task, as it relies on the output generated by synthesis.
Simulation
EDAcation allows you to run testbenches for your design files, which is the process of simulating your design to verify its functionality. The simulation task will take an active testbench file as input and produce a VCD file as output, which can be viewed directly in VSCode. The simulation task can be executed independently of the synthesis and place and route tasks, allowing you to test your design before synthesizing and placing it.
Flashing
EDAcation allows you to flash your design onto a physical FPGA board directly from VSCode. Designs can be flashed both temporarily (to SRAM) and permanently (to flash memory) for rapid prototyping and testing. Note that flashing may require additional hardware, such as a programmer or JTAG interface, depending on your FPGA board.